Semiconductor device and method of manufacturing the same

ABSTRACT

Two semiconductor substrates are first bonded together by means of a metal bump, while respective one-side surfaces on which device patterns are formed are faced each other, and a resin is then filled into a gap between the respective one-side surfaces and thereafter each of the semiconductor substrates is polished and thinned to a prescribed thickness. Furthermore, a via hole and an insulating film are formed; part of a portion in contact with the metal bump, of the insulating film, is opened; the inside of the via hole is filled with a conductor; and an electrode pad is formed on the conductor, to thereby form structures. Finally, a required number of structures are electrically connected with each other through the electrode pad and stacked to thereby obtain a semiconductor device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and itsmanufacturing method and, more particularly, to a technique adapted toeliminate drawbacks arising in association with a thinning in performingthree-dimensional mounting intended for the high density design andmultiple-pin design of semiconductor devices.

[0003] 2. Description of the Related Art Conventionally, various methodshave been proposed as techniques for accomplishing the high densitydesign and multiple-pin design of semiconductor devices. As one method,for example, there is an available method which involves fabricating aprinted wiring board of multilayer structure by means of a build-upmethod and mounting elements such as semiconductor chips on themultilayer printed wiring board so as to obtain a device.

[0004] Also, as another method, there is an available method whichinvolves, instead of fabricating a printed wiring board of multilayerstructure, fabricating a printed wiring board by forming wiring patternson both sides of one insulative substrate, fabricating a device bymounting elements such as semiconductor chips on the wiring patterns ofone surface of the printed wiring board, and performingthree-dimensional mounting by stacking such devices. According to thismethod, it is necessary to electrically interconnect the respectivesemiconductor chips mounted on each of the printed wiring boards. Tothis end, in each of the printed wiring boards are formed through holeswhich pierce the printed wiring board, and wiring patterns formed onboth surfaces of the printed wiring board are electricallyinterconnected through plated films (conductor layers) formed on theinner surfaces of the through holes.

[0005] Also, as still another method of performing three-dimensionalmounting, there is a conceivable method which involves: using a silicon(Si) substrate as a base material layer; forming a hole with a requireddepth in the silicon substrate; forming required device patterns(including circuit patterns, wiring patterns, or the like) after fillingthe hole with a conductor by plating, or the like, so that the devicepatterns are electrically connected to the conductor; covering thedevice patterns with insulating films formed of polyimide resin, or thelike; exposing the conductor by polishing the back surface of thesilicon substrate by means of a back-grinding method, or the like;fabricating a device by providing metal bumps (external connectionterminals) on the exposed conductor; and stacking a required number ofdevices.

[0006] Likewise in this method, it is necessary to electricallyinterconnect each of the devices, and to this end, it is necessary toform through holes in the insulating film of the device, plate the innersurfaces of the through holes, and electrically connect device patternsvia the plated film to metal bumps of an upper-positioned device.

[0007] As described above, various techniques have been proposed astechniques for accomplishing the high density design and multiple-pindesign of semiconductor devices. Among these, in the technique utilizinga build-up method, the thickness of the printed wiring board isconsiderably increased because the printed wiring board is fabricated tohave a multilayer structure. Accordingly, the scale of the wholesemiconductor device in final form becomes large, resulting in a problemin that it is not possible to fully meet the recent requirement forthinning design.

[0008] Also, the method which involves forming a device by means of aninsulative substrate and stacking a required number of devices, isfavorable in terms of the high density design and multiple-pin design,compared with the above technique utilizing a build-up method, because aplurality of semiconductor chips are mutually three-dimensionallymounted. However, this method has a drawback in terms of the thinningdesign in the same manner as described above, because semiconductorchips are interposed between printed wiring boards.

[0009] On the other hand, the method which involves forming a device bymeans of a silicon substrate and stacking a required number of devices,is favorable in terms of the thinning design, because the thickness ofthe silicon substrate is reduced by polishing the back surface thereof.However, this method poses the following problems:

[0010] Namely, in this method, a mechanical polishing such as aback-grinding method is performed to make the silicon substrate thin,and accordingly, there is a limit to the thickness of the siliconsubstrate to be thinned due to mechanical shocks of the mechanicalpolishing. If the silicon substrate is made excessively thin, a problemwould arise in that cracks occur in the silicon substrate and, in somecases, the silicon substrate may be broken or damaged.

[0011] Also, the surface on one side of the silicon substrate, on whichdevice patterns are formed, is formed of an insulating film of polyimideresin, or the like, while the surface on another side is formed of aconductor. Namely, the two surfaces have different coefficients ofthermal expansion, which causes a difference in stresses generatedbetween the one surface and another surface. As a result, for example,when polishing treatment is performed, a problem arises in that thesilicon substrate is warped.

SUMMARY OF THE INVENTION

[0012] An object of the present invention is to provide a semiconductordevice and its manufacturing method, which can eliminate drawbacksarising in association with a thinning (damage to a semiconductorsubstrate, occurrence of cracks, warping of a semiconductor substrate,or the like) in performing three-dimensional mounting intended for thehigh density design and multiple-pin design.

[0013] To attain the above object, according to one aspect of thepresent invention, there is provided a method of manufacturing asemiconductor device, which includes the steps of: bonding, by means ofa metal bump, two semiconductor substrates, on respective one-sidesurfaces of which a conductor layer patterned to a required shape isformed, while facing the respective one-side surfaces, each other;filling, with an insulating resin, a gap between the respectiveconductor layers bonded by means of the metal bump; polishing each ofexposed side surfaces of the semiconductor substrates to thereby thineach of the semiconductor substrates to a prescribed thickness; forminga via hole which reaches the metal bump, in a required place of each ofthe thinned semiconductor substrates; forming an insulating film on thesurface of each of the semiconductor substrates including an innersurface of the formed via hole; opening at least part of a portion incontact with the metal bump, of the insulating film formed within thevia hole; filling an inside of the via hole with a conductor and furtherforming, on the insulating film, an electrode pad patterned to arequired shape and electrically connected to the conductor; and stackinga structure obtained by the above-described steps, by a required number,by electrically connecting respective structures with each other throughthe electrode pad.

[0014] According to the method of manufacturing a semiconductor deviceaccording to this aspect, it is possible to accomplish a thinning designas the whole semiconductor device in a three-dimensionally mountedconfiguration which is finally manufactured, because two semiconductorsubstrates are first bonded together by means of a metal bump, whilerespective one-side surfaces, on which conductor layers (devicepatterns) are formed are faced each other, and an insulating resin isthen filled into the gaps between the semiconductor substrates, andthereafter the thickness of each of the substrates is reduced bypolishing both surfaces, i.e., each of the exposed side surfaces of thesemiconductor substrates.

[0015] Also, since the insulating resin is filled into the gap betweenthe facing conductor layers of the semiconductor substrates, it ispossible to effectively absorb and buffer mechanical shocks caused bythe polishing (thinning treatment) of each substrate, with the aid ofthe insulating resin. Namely, the insulating resin functions as acushion (a buffer layer). As a result, even in the case thatsemiconductor substrates are thinned to a level close to the limit ofthe state-of-the art, it is possible to eliminate drawbacks as seen inthe prior art, such as the occurrence of cracks and damage to asubstrate. In other word, it is possible to improve the crack resistanceof the semiconductor substrate.

[0016] Furthermore, since the object of polishing (thinning treatment)is a structure obtained by sticking the two semiconductor structurestogether symmetrically as if reflected in a mirror, while the respectiveone-side surfaces on which the conductor layers (device patterns) areformed are faced each other, it is possible to eliminate drawbacks asseen in the prior art, such as warping of a semiconductor substratecaused by a difference in stresses generated between the one surface andanother surface of the substrate. In other words, it is possible toremedy the warping of the semiconductor substrate.

[0017] Also, according to another aspect of the present invention, thereis provided a method of manufacturing a semiconductor device, whichincludes the steps of: bonding, by means of a metal bump, twosemiconductor substrates, on respective one-side surfaces of which aconductor layer patterned to a required shape is formed, while facingthe respective one-side surfaces, each other; filling, with aninsulating resin, a gap between the respective conductor layers bondedby means of the metal bump; polishing each of exposed side surfaces ofthe semiconductor substrates to thereby thin only one of thesemiconductor substrates to a prescribed thickness; forming a via holewhich reaches the metal bump, in a required place of the thinnedsemiconductor substrate; forming an insulating film on the surface ofeach of the semiconductor substrates including an inner surface of theformed via hole; opening at least part of a portion in contact with themetal bump, of the insulating film formed within the via hole; andfilling an inside of the via hole with a conductor and further forming,on the insulating film on the thinned semiconductor substrate, anelectrode pad patterned to a required shape and electrically connectedto the conductor.

[0018] According to the method of manufacturing a semiconductor deviceaccording to this aspect, in the same manner as in the method ofmanufacturing a semiconductor device according to the above-describedaspect, it is possible to accomplish a thinning design as the wholesemiconductor device in a three-dimensionally mounted configurationwhich is finally manufactured, because two semiconductor substrates arefirst bonded together by means of a metal bump, while respectiveone-side surfaces on which conductor layers (device patterns) are formedare faced each other, and an insulating resin is then filled into thegaps between the silicon substrates, and thereafter the thickness of onesubstrates is reduced by polishing each exposed surface of the siliconsubstrates. Also, owing to the presence of the insulating resin whichfunctions as a buffer layer, it is possible to buffer mechanical shockscaused by the polishing (thinning treatment), and thus to eliminatedrawbacks such as the occurrence of cracks in the semiconductorsubstrate. Furthermore, since the object of polishing (thinningtreatment) is a structure obtained by sticking the two semiconductorstructures together symmetrically as if reflected in a mirror, while therespective one-side surfaces on which the conductor layers (devicepatterns) are formed are faced each other, it is possible to eliminatedrawbacks, such as warping of a semiconductor substrate caused by adifference in stresses generated between the one surface and anothersurface of the substrate.

[0019] Also, according to still another aspect of the present invention,there is provided a semiconductor device manufactured by a method ofmanufacturing a semiconductor device according to each of the aboveaspects.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a sectional view showing the structure of asemiconductor device according to an embodiment of the presentinvention;

[0021]FIG. 2A to FIG. 2K are sectional views showing the manufacturingsteps of the semiconductor device shown in FIG. 1;

[0022]FIG. 3 is a sectional view showing the structure of asemiconductor device according to another embodiment of the presentinvention; and

[0023]FIG. 4A to FIG. 4G are sectional views showing the manufacturingsteps of the semiconductor device shown in FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024]FIG. 1 schematically shows the sectional structure of asemiconductor device according to an embodiment of the presentinvention.

[0025] The semiconductor device 10 according to this embodiment has athree-dimensionally mounted configuration formed by stacking structures20 a, 20 b, 20 c in three stages, as shown in the figure. In each of thestructures 20 a, 20 b, 20 c, numerals 21 and 22 denote a siliconsubstrate thinned to a prescribed thickness, respectively; numerals 23and 24 denote a conductor layer which is formed on one surface of thecorresponding silicon substrate 21, 22, respectively, and which involvesdevice patterns including required circuit patterns, wiring patterns, orthe like; the numeral 25 denotes a metal bump which bonds the twosilicon substrates 21, 22 through each of the conductor layers 23, 24 aswill be described later; and numeral 26 denotes an insulative resinlayer formed by being filled into a gap between the conductor layers 23,24 bonded together by means of the metal bump 25. The metal bump 25functions as a metal post, and the insulative resin layer 26 functionsas a buffer layer to cushion mechanical shocks caused by the thinningtreatment of a silicon substrate as will be described later, and alsofunctions as a reinforcing agent.

[0026] Also, numeral 27 denotes an insulating film which functions as aprotective film for each of the structures 20 a, 20 b, 20 c; numeral 28denotes a conductor filled into a via hole formed in each of the siliconsubstrates 21, 22; and numeral 29 denotes an electrode pad formed oneach of the insulating films 27 and electrically connected to theconductor 28. The conductor 28 is electrically connected to the metalbump 25 through an opening (indicated by OP in FIG. 2F) formed in partof the insulating film 27 within the via hole. Therefore, the electrodepads 29 formed on both surfaces of each of the structures 20 a, 20 b, 20c are interconnected through the conductor 28 and the metal bump 25.

[0027] The thickness of each of the structures 20 a, 20 b, 20 c isselected to be approximately 50 μm; the thickness (t1, t2) of thethinned silicon substrates 21, 22 is selected to be in the range of 3 μmto 20 μm; and the thickness of the insulative resin layer (buffer layer)26 is selected to be approximately 30 μm.

[0028] Also, numerals 30 a, 30 b and 30 c denote a metal bump bonded tothe electrode pad 29 on the side of one surface (lower side in theillustrated example) of the corresponding structures 30 a, 20 b, 20 c.Among these, the metal bump 30 a bonded to the electrode pad 29 of thelowest-positioned structure 20 a functions as an external terminal ofthis device 10. Also, numeral 31 denotes an insulative resin layerfilled as an underfill into gaps between the stacked structures 20 a, 20b, 20 c.

[0029] In the above-described constitution, as the materials whichconstitute the metal bumps 25, 30 a, 30 b and 30 c, Pb-free solders suchas silver-tin (Ag—Sn) are used, in addition to eutectic solders, such asgenerally-used lead-tin (Pb—Sn). Alternatively, gold (Au), silver (Ag),copper (Cu), indium (In) or its alloys (In—Pb, In—Sn, or the like),nickel (Ni), and the like, may be used. Also, each of the bumps 25, 30a, 30 b and 30 c may be formed by a generally-used plating methodutilizing photo processes, or may be a ball bump such as a stud bumpformed by means of wire bonding techniques.

[0030] Also, Cu is typically used as the material for the devicepatterns (conductor layers 23, 24) including circuit patterns and wiringpatterns. In order to further increase electrical conductivity andimprove the reliability of connection to the metal bump 25, it ispreferable to apply a coating of Au, Sn, or the like, for example.Furthermore, Au, Cu, Ni, chromium (Cr), aluminum (Al), or the like, isused as the material for the conductor 28 and the electrode pad 29.Also, epoxy resin, polyimide resin, or the like is used as the materialfor the insulative resin layer (buffer layer) 26 and the insulativeresin layer (underfill material) 31. Furthermore, as the material forthe insulating film (protective film) 27, photosensitive resin such aspolyimide resin, epoxy resin, or the like, silicon oxide films formed bychemical vapor deposition (CVD) process, phosphorous silicate glass(PSG), or the like, is used.

[0031] Although in this embodiment the external connection terminal(metal bump 30 a) is provided as shown in FIG. 1, it is not alwaysnecessary to provide the external connection terminal. This is becausesuch an external connection terminal may be provided immediately beforethe semiconductor device 10 is mounted on a mother board such as aprinted circuit board, in actual use. Therefore, as a finalconfiguration of the semiconductor device 10, it is necessary only thatthe electrode pad 29 be exposed so that the external connection terminal(metal bump 30 a) can be bonded.

[0032] Hereinafter, a method of manufacturing the semiconductor device10 according to the present embodiment will be described with referenceto FIG. 2A to FIG. 2K which show the manufacturing steps in sequence.

[0033] First, in the first step (FIG. 2A), two silicon substrates 21aand 22a, on respective one-side surfaces of which a conductor layer 23,24 patterned to a required shape is formed, are bonded by means of ametal bump 25, while the respective one-side surfaces on which theconductor layer 23, 24 is formed are faced each other.

[0034] Concretely, two relatively thick silicon substrates 21 a, 22 ahaving a thickness of approximately 100 μm to 300 μm are first prepared,and on respective one-side surfaces of the silicon substrates 21 a, 22 aare formed required device patterns (conductor layers 23, 24), by meansof a well-known photolithography technique. Subsequently, a plurality ofmetal bumps 25 are bonded to prescribed positions on the conductor layer23 of one silicon substrate 21 a, for example, by ultrasonic bonding(i.e., bonding method which utilizes the thermal action or cavitationeffect of ultrasonic waves), thermocompression bonding (wire bondingmethod, reflow soldering method), or the like. Subsequently, the twosilicon substrates 21 a, 22 a are bonded together through the conductorlayers 23, 24 by means of the metal bump 25, while the oneside surfaceto which the metal bump 25 of this silicon substrate 21a is bonded isfaced with the one-side surface on which the conductor layer 24 of theother silicon substrate 22 a is formed. Namely, a structure in which thetwo silicon substrates 21 a, 22 a are stuck together through the metalbump 25 is obtained.

[0035] In the next step (FIG. 2B), the structure obtained in thepreceding step (formed by sticking the two silicon substrates 21 a, 21 btogether through the metal bump 25) is placed in a vacuum chamber and aninsulative resin such as epoxy resin is then filled into a gap betweenthe conductor layers 23, 24 bonded by the metal bump 25, to thereby forman insulative resin layer 26 having a thickness of approximately 30 μm.

[0036] In the next step (FIG. 2C), both surfaces of the structureobtained in the preceding step, i.e., the surfaces of the exposed sidesof the silicon substrate 21 a, 22 a, are thinned by performingmechanical polishing such as a back-grinding method, so as to constitutesilicon substrates 21, 22 having a thickness (t1≈t2) of approximately 3μm to 20 μm. The portions indicated by broken lines in the figurerepresent portions removed by the polishing.

[0037] In the next step (FIG. 2D), a via hole VH reaching the metal bump25 is formed in a required place of each of the semiconductor substrates21, 22 thinned in the preceding step. The via hole VH can be formed bydrilling, for example, by means of a CO₂ laser, a YAG laser, an excimerlaser, or the like, or by etching, for example, by means of a plasmaetcher.

[0038] In the next step (FIG. 2E), by means of a CVD process, a siliconoxide film (SiO₂), i.e., an insulating film 27, is formed on the surfaceof the silicon substrates 21, 22 including the inner surface of the viahole VH formed therein.

[0039] The insulating film 27 is formed to electrically insulate aconductor layer to be filled in the via hole VH in a subsequent stepfrom the silicon substrates 21, 22, and also functions as a protectivefilm as described above.

[0040] Although in this step a silicon oxide film is formed as theinsulating film 27, for example, a phosphorus silicate glass (PSG) maybe formed by means of CVD method, in place of the silicon oxide film.Alternatively, it is also possible to form the insulating film 27 bycoating a resin (in particular, a photosensitive resin), such aspolyimide resin, epoxy resin, or the like, on the whole surface.

[0041] In the next step (FIG. 2F), among the respective insulating films27 on both surfaces formed in the preceding step, at least part of aportion in contact with the metal bump 25, of the insulating film 27formed within the via hole VH, is opened (opening OP). The opening OPcan be formed, by the same treatment as in the step of FIG. 2D, i.e., bydrilling, for example, by means of a CO₂ laser, a YAG laser, or thelike, or by etching, for example, by means of a plasma etcher.

[0042] As a result, a portion corresponding to the opening OP of theinsulating film 27 in the via hole VH, i.e., part of the metal bump 25is exposed.

[0043] Although in this step, the opening OP of the insulating film 27is formed by a laser, plasma etching, or the like, where the insulatingfilm 27 is formed by coating a photosensitive resin, it is also possibleto form the opening OP by a well-known photolithography technique.

[0044] In the next step (FIG. 2G), by means of electroless plating orelectrolytic plating, for example, a conductor layer CL is formed tofill the via hole VH formed in each of the silicon substrates 21, 22(part of the insulating film 27 formed therein opens (opening OP)).

[0045] Concretely, the whole surface is first subjected to electrolessnickel (Ni)plating, and then, the nickel layer is subjected toelectroless gold (Au)plating, or to flash plating (plating of very smallthickness) by electrolytic Au plating using the Ni layer as a powersupply layer. Subsequently, electrolytic copper (Cu) plating isperformed to fill the via hole VH using the Au layer as a power supplylayer, to thereby form a three-layer (Ni/Au/Cu) conductor layer CL. TheNi layer in the conductor layer CL is intended to increase the adhesionto the underlying insulating film (SiO₂) 27, and the Au layer is formedto lower electric resistance during electrolytic Cu plating.

[0046] In the conductor layer CL thus formed, a conductor 28 buried inthe via hole, VH is used to form an electrode pad on this conductor in asubsequent step. Also, since the treatment which is little more thanplating is performed in this step, a conductor layer 28 a is formed asshown in the figure also in portions other than the via hole VH on theinsulating film 27.

[0047] In the next step (FIG. 2H), the whole surface is made flat byremoving the unnecessary conductor layer 28 a formed in portions otherthan the via hole VH on the insulating film 27 by means of mechanicalpolishing, chemical mechanical polishing (CMP), or the like, until thetop end surface of the conductor 28 buried in the via hole VH on theinsulating film 27 is exposed.

[0048] In the next step (FIG. 2I), on each of the insulating films 27 onboth sides is formed an electrode pad 29 of a required shape, so as tobe electrically connected to the conductor 28 buried in the via hole VH.

[0049] The electrode pad 29 can be formed, for example, by coating orforming a resist (not shown) on the whole surface, patterning the resistto a required shape, and performing a sputtering of Cu, Al, Au, Cr, orthe like, by means of the resist as a mask. Alternatively, any platingmay be performed in place of the sputtering.

[0050] As a result of the above-described steps, each of the structures30 a, 20 b, 20 c which constitute the semiconductor device 10 isfabricated. Although in the example of FIG. 2I, the structure 20 a ofthe lowest stage is shown, the other structures 20 b, 20 c can also besimilarly fabricated by the steps shown in FIG. 2A to FIG. 2I. Note, thestructures 20 b, 20 c differ from the structure 20 a in that theposition where the via hole VH is formed in the step of FIG. 2D isdifferent from that of the structure 20 a.

[0051] In the next step (FIG. 2J), a metal bump 30 a is bonded to theelectrode pad 29 on the lower side of the structure 20 a formed in thepreceding step. Although not shown in the figure, metal bumps 30 b, 30 care also similarly bonded to the other structures 20 b, 20 c. In thiscase, as described above, it is not always necessary to provide themetal bump 30 a on the structure 20 a of the lowest stage.

[0052] Solder, Au, Ag, In, or the like, is used as the material for themetal bumps 30 a, 30 b, 30 c. For example, where In is used, because ofthe considerably low melting point of this metal compared with othermetals, there is a merit in that, in performing bump bonding, it ispossible to suppress a thermal effect on the resin layer (in this case,the insulative resin layer 26) in the structure.

[0053] In the final step (FIG. 2K), the structures 30 a, 20 b, 20 c towhich the metal bumps 30 a, 30 b, 30 c are bonded, respectively, arestacked and electrically interconnected by thermocompression bonding, orthe like, through the metal bumps 30 b, 30 c. The metal bump 30 a of thestructure 20 a of the lowest stage is used as an external connectionterminal.

[0054] Furthermore, an insulative resin as an underfill is filled intothe gap between the stacked structures 30 a, 20 b, 20 c , whereby thesemiconductor device 10 (FIG. 1) of this embodiment is obtained.

[0055] As described above, according to the semiconductor device 10(FIG. 1) of this embodiment and its manufacturing method (FIG. 2A toFIG. 2K), it is possible to accomplish a thinning design as the wholesemiconductor device 10 in a three-dimensionally mounted configurationto be finally manufactured, because the silicon substrates 21 a, 22 aare bonded together by means of the metal bump 25, while the respectiveone-side surfaces on which the device pattern (the conductor layer 23,24) is formed are faced each other; the insulative resin (buffer layer )26 is filled into the gap between the silicon substrates 21 a, 22 a ;and thereafter the thickness of each of the substrates is reduced bypolishing the respective exposed surfaces of the silicon substrates 21a, 22 a (the silicon substrates 21, 22).

[0056] Also, since the buffer layer 26 is interposed between the facingconductor layers 23, 24 of the silicon substrates 21 a, 22 a , it ispossible to effectively absorb and buffer mechanical shocks caused bythe polishing of each substrate, with the aid of the buffer layer 26.This contributes to an improvement in the crack resistance of thesilicon substrates 21, 22. In other words, even if the siliconsubstrates are thinned to a level close to the limit of the state-of-theart, it is possible to eliminate drawbacks as seen in the prior art,such as occurrence of cracks, damage to a substrate, or the like.

[0057] Furthermore, since the object of polishing is the structureobtained by sticking the two silicon structures 21 a, 22 a togethersymmetrically as if reflected in a mirror, while the respective one-sidesurfaces on which the device pattern (the conductor layer 23, 24) isformed are faced each other, it is possible to eliminate drawbacks asseen in the prior art, such as a warping of the silicon substrate causedby a difference in stresses generated between the one surface andanother surface of the substrate.

[0058] Furthermore, since the thickness of each of the siliconsubstrates 21, 22 is reduced to approximately 3 μm to 20 μm, it becomeseasy to form the via hole VH in the thinned silicon substrates (FIG. 2C,FIG. 2D).

[0059] In the above-described embodiment, the explanation is made withrespect to the case where the conductor layer CL of Ni/Au/Cu is formedby means of electroless plating and electrolytic plating in the step ofFIG. 2G. However, it would be obvious that the method of forming theconductor layer CL is not limited to the above case. For example, arequired film may be formed by sputtering, in place of the electrolessplating.

[0060] As a concrete example, Cr, for example, is deposited bysputtering on the whole surface of each insulating layer 27 includingthe inner surface of the via hole VH and the surface of the exposedmetal bump 25; Cu is further deposited on the Cr layer by sputtering, soas to form a metal thin film of two-layer structure; and a metal layerof Cu is formed on the entire surface by electrolytic plating, by meansof the metal thin film as a power supply layer, whereby it is possibleto form a conductor layer of Cr/Cu. In this case, as with the Ni layerin the above-described conductor layer CL, the Cr layer which is theunderlayer portion of the metal thin layer is formed to increaseadhesion to the underlying insulating film 27.

[0061] Also, in the above-described embodiment, the explanation is madewith respect to the case where the structures 20 a, 20 b, 20 c arestacked in three stages by aligning the positions of the metal bumps 25and the electrode pads 29 of each structure. However, as a matter ofcourse, it is not always necessary to align the positions of the metalbumps 25 and the positions of the electrode pads 29 (i.e., the positionsof the metal bumps 30 a, 30 b, 30 c ), and as a matter of course, thenumber of stages to be stacked is not limited to three.

[0062] Also, it is not always necessary to stack such a structure inmultiple stages, and the structure may be in a single stage depending onthe required conditions. An example of such a single-stage structure isshown in FIG. 3.

[0063]FIG. 3 schematically shows the sectional structure of thesemiconductor device according to another embodiment of the invention.

[0064] The semiconductor device 40 according to this embodiment differsfrom the semiconductor device 10 according to the above-describedembodiment (FIG. 1 and FIG. 2A to FIG. 2K) in that the structure(equivalent to each of the structures 20 a, 20 b, 20 c shown in FIG. 2K)is not stacked in multiple stages, and in that, in polishing each of thesilicon substrates 42 a, 42 b from both sides as will be describedlater, only one silicon substrate is thinned to a prescribed thickness(T1), while the thickness of the other silicon substrate is not reducedso as to have a certain thickness (T2). Since the other features arebasically the same as those of the structure 20 c of the highest stageshown in FIG. 1, the description thereof is omitted.

[0065] Hereinafter, a method of manufacturing the semiconductor device40 according to this embodiment will be described with reference to FIG.4A to FIG. 4G which show the manufacturing steps in sequence.

[0066] First, in the first step (FIG. 4A), in the same manner as withthe treatment performed in the steps of FIG. 2A and FIG. 2B, two siliconsubstrates 41 a, 42 a are bonded together by means of a metal bump 45,while respective one-side surfaces on which a conductor layer 43, 44(device pattern) is formed are faced each other, and an insulative resin46 as a buffer layer is filled into a gap between the surfaces.

[0067] In the next step (FIG. 4B), both surfaces of the structureobtained in the preceding step (i.e., respective one-side surfaces towhich the silicon substrate 41 a, 42 a is exposed) are polished by meansof a back grinding method in such a manner that only one siliconsubstrate 41 a is thinned to a prescribed thickness T1 (approximately 3μm to 20 μm) to thereby obtain a silicon substrate 41, while for theother silicon substrate 42 a, the amount of polishing is relativelyreduced to have a certain thickness T2 (approximately 100 μm to 300 μm)to thereby obtain a silicon substrate 42. The portions indicated bybroken lines in the figure represent portions removed by the polishing.

[0068] In the next step (FIG. 4C), a via hole VH which reaches the metalbump 45 is formed in a required place of one semiconductor substrates 41thinned in the preceding step. In the same manner as in the treatmentperformed in the above-described step of FIG. 2D, the via hole VH can beformed by drilling, for example, by means of a laser, or by etching, forexample, by means of a plasma etcher.

[0069] In the next step (FIG. 4D), in the same manner as in thetreatment performed in the above-described steps of FIG. 2E and FIG. 2F,an insulating film 47 such as a silicon oxide film is formed by means ofCVD process, for example, on the surface of each of the siliconsubstrates 41, 42 including the inner surface of the via hole VH.Furthermore, by means of a laser or a plasma etcher, for example, atleast part of the portion in contact with the metal bump 45, of theinsulating film 47 formed in the via hole VH, is opened (opening OP). Asa result, part of the metal bump 45 is exposed.

[0070] In the next step (FIG. 4E), in the same manner as in thetreatment performed in the above-described steps of FIG. 2G and FIG. 2H,a conductor layer is formed by plating, for example, so, as to fill thevia hole VH formed in one silicon substrates 41 (part of the insulatingfilm 47 formed therein opens (opening OP)), and a conductor 48 embeddedin the via hole VH is formed by removing the unnecessary conductor layerformed in portions other than the via hole VH, by means of mechanicalpolishing, or the like.

[0071] In the next step (FIG. 4F), on the insulating film 47 on onesilicon substrate 41 is formed an electrode pad 49 of a required shape,to as to be electrically connected to the conductor 48 embedded in thevia hole VH. The electrode pad 49 can be formed by sputtering, plating,or the like, in the same manner as in the treatment performed in theabove-described step of FIG. 2I.

[0072] In the final step (FIG. 4G), a metal bump 50 as an externalconnection terminal is bonded to the electrode pad 49 formed in thepreceding step. As a result, the semiconductor device 40 (FIG. 3) ofthis embodiment is obtained.

[0073] According to the embodiment shown in FIG. 3 and FIG. 4A to FIG.4G, as in the case of the above-described embodiment (FIG. 1 and FIG. 2Ato FIG. 2K), it is possible to accomplish a thinning design as the wholesemiconductor device 40 to be finally manufactured, because the siliconsubstrates 41 a, 42 a are bonded together by means of the metal bump 45,while the respective one-side surfaces on which the device pattern (theconductor layer 43, 44) is formed are faced each other; an insulativeresin (buffer layer) 46 is filled into the gap between the siliconsubstrates 41 a, 42 a; and each of the exposed surfaces of the siliconsubstrates 41 a, 42 a is thinned (the silicon substrates 41, 42).

[0074] Also, because of the presence of the insulative layer (the bufferlayer) 46, it is possible to effectively absorb and buffer mechanicalshocks caused by the polishing of each of the substrates 41 a, 42 a, andhence it is possible to eliminate drawbacks such as occurrence ofcracks, or the like, in the silicon substrates 41, 42. Furthermore,since the object of polishing is the structure obtained by sticking thetwo silicon structures 41 a, 42 a together symmetrically as if reflectedin a mirror, while the respective one-side surfaces on which the devicepattern (the conductor layer 43, 44) is formed are faced each other, itis possible to eliminate drawbacks such as a warping of the siliconsubstrate caused by a difference in stresses generated between the twosurfaces. Similarly, since the thickness of the silicon substrate 41 isreduced to approximately 3 μm to 20 μm, it becomes easy to form the viahole VH in the thinned silicon substrates (FIG. 4B, FIG. 4C).

What is claimed is:
 1. A method manufacturing a semiconductor device,comprising the steps of: bonding, by means of a metal bump, twosemiconductor substrates, on respective one-side surfaces of which aconductor layer patterned to a required shape is formed, while facingsaid respective one-side surfaces, each other; filling, with aninsulating resin, a gap between the respective conductor layers bondedby means of the metal bump; polishing each of exposed side surfaces ofsaid semiconductor substrates to thereby thin each of the semiconductorsubstrates to a prescribed thickness; forming a via hole which reachesthe metal bump, in a required place of each of said thinnedsemiconductor substrates; forming an insulating film on the surface ofeach of said semiconductor substrates including an inner surface of saidformed via hole; opening at least part of a portion in contact with saidmetal bump, of the insulating film formed within said via hole; fillingan inside of said via hole with a conductor and further forming, on saidinsulating film, an electrode pad patterned to a required shape andelectrically connected to the conductor; and stacking a structureobtained by the above-described steps, by a required number, byelectrically connecting respective structures with each other throughsaid electrode pad.
 2. The method according to claim 1, furthercomprising, after the step of stacking the required number ofstructures, the step of bonding a metal bump as an external connectionterminal to the electrode pad formed on an exposed side surface of thelowest-positioned structure.
 3. The method according to claim 1, whereinin the step of stacking the required number of structures, respectiveelectrode pads facing each other, of an upper-positioned structure and alower-positioned structure, are bonded by means of a metal bump.
 4. Themethod according to claim 3, wherein after the step of stacking therequired number of structures, an insulating resin is filled into gapsbetween the stacked structures.
 5. The method according to claim 1,wherein conductor layers to be formed on the respective one-sidesurfaces of said two semiconductor substrates are patterned so as tomutually exhibit the same shape when arranged to be faced each otherduring bonding.
 6. The method according to claim 1, wherein in the stepof thinning each of said semiconductor substrates to a prescribedthickness, the prescribed thickness is selected in the range of 3 μm to20 μm.
 7. A method of manufacturing a semiconductor device, comprisingthe steps of: bonding, by means of a metal bump, two semiconductorsubstrates, on respective one-side surfaces of which a conductor layerpatterned to a required shape is formed, while facing said respectiveone-side surfaces, each other; filling, with an insulating resin, a gapbetween the respective conductor layers bonded by means of the metalbump; polishing each of exposed side surfaces of said semiconductorsubstrates to thereby thin only one of the semiconductor substrates to aprescribed thickness; forming a via hole which reaches the metal bump,in a required place of said thinned semiconductor substrate; forming aninsulating film on the surface of each of said semiconductor substratesincluding an inner surface of said formed via hole; opening at leastpart of a portion in contact with said metal bump, of the insulatingfilm formed within said via hole; and filling an inside of said via holewith a conductor and further forming, on the insulating film on saidthinned semiconductor substrate, an electrode pad patterned to arequired shape and electrically connected to the conductor.
 8. Themethod according to claim 7, further comprising, after the step offorming the electrode pad, the step of bonding a metal bump as anexternal connection terminal to the electrode pad.
 9. A semiconductordevice manufactured by the method of manufacturing a semiconductordevice according to claim
 2. 10. A semiconductor device manufactured bythe method of manufacturing a semiconductor device according to claim 8.